The present invention relates to an image size converter for reducing or enlarging image data.
A conventional image size converter such as that shown in FIG. 1 includes a Digital Differential Analyzer (DDA). The DDA is a known circuit for generating coordinate values from an initial scale value and an increment scale value. The DDA includes adder 14, scale register 15 in which a reduction or enlargement ratio of an image size is set, and accumulator 16 in which "0" is set as an initial value and then a decimal part is set.
The image size converter also includes logic circuitry connecting the DDA to a source register 11 and a conversion pattern register 13. AND gate 1 gates a carry signal from adder 14 during reduction of the image in the reduction mode, and AND gate 2 gates a carry signal from adder 14 during enlargement of the image in the enlargement mode. The logic circuitry also includes OR gate 4 for continuously supplying a shift signal to source shift register 11 (to be described later) in the reduction mode, OR gate 3 for continuously supplying a shift signal to destination register 13 in the enlargement mode, and AND gates 6 and 5 for gating the shift signals from OR gates 4 and 3, respectively. Source shift register 11 stores image data, data generator 12 (e.g., OR gates) receives an image dot pattern from register 11 and generates an image data pattern representing an enlarged or reduced image dot pattern, and destination register 13 stores image data output from data generator 12.
In order to reduce image data in the circuit of FIG. 1, image data output from source shift register 11 in units of dots is extracted (or logically ORed) by data generator 12 at a predetermined rate. Image enlargement is performed by copying the same image data to destination shift register 11 until a significant carry signal is supplied thereto. Image data enlargement and reduction in the conventional image size converter will be described below. It should be noted that the circuit in FIG. 1 is operated according to the normal logic, i.e., active high.
To understand the operation of the system of FIG. 1 in the reduction mode, assume that the image size is to be reduced to 1/3. In this case, value "1/3" is set in scale register 15, and "0" is set as the initial value in accumulator 16. Adder 14 adds "0" and "1/3" and feeds back the sum "1/3" to accumulator 16. The first addition does not cause generation of a carry signal. In the second addition, "1/3" in accumulator 16 is added to "1/3" in scale register 15, so that the resultant sum is "2/3". As is apparent from the resultant sum, no carry signal is generated. In the third addition, "2/3" in the accumulator 16 is added to "1/3" in scale register 15, and the resultant sum is "1". In this case, a carry from the decimal part to the integer part occurs, and a significant carry signal is output. Since the addition result represents "1" (="3/3"), the decimal part is "0", and "0" is set again in accumulator 16. The above operations are then repeated. When the scale is set to be 1/3, adder 14 generates a significant (logic "1") carry signal "1" for every three additions. More specifically, adder 14 sequentially generates logic "0", logic "0", logic "1", logic "0", logic "0", logic "1", etc. In the first addition output from adder 14, a carry signal of logic "0" is supplied to AND gate 1, and at the same time a reduction mode signal of logic "1" is supplied to AND gate 1. The reduction mode signal of logic "1" is also supplied to OR gate 4. OR gate 4 continuously supplies signals of high level to AND gate 6, and thus AND gate 6 supplies the shift signal to source shift register 11 in response to the clock signal. Register 11 outputs 1-bit at a time of an image dot pattern in response to the clock signal. Data generator 12 ORs the 1-bit output with the most significant fit (MSB) of register 11, and supplies the OR product to register 13. Register 13 stores the OR product and feeds it back to generator 12. The above operation is repeated in correspondence with the clock signal.
At the same time AND gate 1 receives a carry signal of logic "0", and AND Gate 5 does not supply the shift signal to destination register 13 since the signal output from OR gate 3 is set at logic "0". In the second addition, no carry occurs from the decimal part to the integer part, and the same operation as in the first addition is performed. In the third addition, a significant (logic "1") carry signal is output from adder 14. The carry signal of logic "1" is supplied to AND gate 5 through OR gate 3. AND gate 5 supplies the shift signal (i.e., the carry signal of logic "1") to destination register 13 at the clock signal, and the contents of register 13 are shifted by one bit. In this state, a 3-bit image dot pattern from register 11 is logically ORed with each other by generator 12, and the result is held as the MSB of register 13. In this manner, the above operations are repeated to reduce the image data by 1/3.
In the enlargement mode, an enlargement signal of logic "1" is supplied to AND gate 2 and OR gate 3. OR gate 3 outputs a signal of logic "1" so that AND gate 5 supplies a clock signal to destination register 13. Register 13 performs shifting in correspondence with the clock signal. In the first addition, since the carry signal is set at logic "0", AND gate 2 generates this signal, i.e., a logic "0". The signal of logic "0" is supplied to AND gate 6 through OR gate 4, and AND gate 6 does not supply the clock signal to source register 11. Information is not shifted through register 11. An image dot from register 11 is supplied to data generator 12, and generator 12 supplies its data to register 13. The same operation as in the first addition is repeated in the second addition. In the third addition, since the carry signal of logic "1" is output, this signal is supplied to register 11 through AND gate 2, OR gate 4, and AND gate 6. As a result, register 11 is shifted by one bit, and the next image dot pattern is generated. In the case of 3.times. enlargement, register 13 is shifted three times while register 11 is shifted once. Therefore, the same image dot from register 11 is copied in register 13 three times.
As is apparent from the above description, reduction or enlargement in units of dots is performed in the conventional image size converter. For this reason, in industrial fields requiring high-speed image size conversion, e.g., in an image retrieval system connected to an optical disk, a long waiting time is required for an operator since the processing speed is very low.